Isolation process and structure for CMOS imagers

ABSTRACT

A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices and,in particular, to high quantum efficiency CMOS image sensors.

BACKGROUND OF THE INVENTION

CMOS imagers are known in the art. A top-down view of a semiconductorwafer fragment of an exemplary CMOS sensor pixel four-transistor (4T)cell 10 is illustrated in FIG. 1. As it will be described below, theCMOS sensor pixel cell 10 includes a photo-generated charge accumulatingarea 21 in an underlying portion of the substrate. This area 21 isformed as a pinned diode 11 (FIG. 2). The pinned photodiode is termed“pinned” because the potential in the photodiode is pinned to a constantvalue when the photodiode is fully depleted. It should be understood,however, that the CMOS sensor pixel cell 10 may include a photogate orother image to charge converting device, in lieu of a pinned photodiode,as the initial accumulating area 21 for photo-generated charge.

The CMOS image sensor 10 of FIG. 1 has a transfer gate 30 fortransferring photoelectric charges generated in the charge accumulatingregion 21 to a floating diffusion region (sensing node) 25. The floatingdiffusion region 25 is further connected to a gate 50 of a sourcefollower transistor. The source follower transistor provides an outputsignal to a row select access transistor having gate 60 for selectivelygating the output signal to terminal 32. A reset transistor having gate40 resets the floating diffusion region 25 from a supply voltage appliedat a source/drain region between gates 40 and 50 to a specified chargelevel before each charge transfer from the charge accumulating region21.

A cross-sectional view of the exemplary CMOS image sensor 10 of FIG. 1taken along line 2-2′ is illustrated in FIG. 2. The charge accumulatingregion 21 is formed as a pinned photodiode 11 which has a photosensitiveor p-n-p junction region formed by a p-type layer 24, an n-type region26 and the p-type substrate 20. The pinned photodiode 11 includes twop-type regions 20, 24 so that the n-type photodiode region 26 is fullydepleted at a pinning voltage. Impurity doped source/drain regions 22(FIG. 1), preferably having n-type conductivity, are provided on eitherside of the transistor gates 40, 50, 60. The floating diffusion region25 adjacent the transfer gate 30 is also preferably n-type.

Generally, in CMOS image sensors such as the CMOS image sensor cell 10of FIGS. 1-2, incident light causes electrons to collect in region 26. Amaximum output signal, which is produced by the source followertransistor having gate 50, is proportional to the number of electrons tobe extracted from the region 26. The maximum output signal increaseswith increased electron capacitance or acceptability of the region 26 toacquire electrons. The electron capacity of pinned photodiodes typicallydepends on the doping level of the image sensor and the dopantsimplanted into the active layer.

FIG. 2 also illustrates trench isolation regions 15 formed in asubstrate layer 20 in which the charge accumulating region 21 is formed.The substrate layer 20 may be an epitaxial layer provided over a siliconbase layer. The trench isolation regions 15 are typically formed using aconventional STI process or by using a Local Oxidation of Silicon(LOCOS) process. Trench isolation regions 15 provide a physical barrierbetween adjacent pixels and help isolate pixels optically andelectrically from one another. For example, as shown in FIG. 2, trenchisolation region 15 provides surface electrical isolation of the pinnedphotodiode 11 of pixel region A from the photosensitive elements ofadjacent pixel region B.

Another problem associated with the formation of the above-describedtrench isolation regions 15 is that, when ions are implanted in thesubstrate close to bottom 17 and edges or sidewalls 16 (FIG. 2) of thetrench, current leakage can occur at the junction between the activedevice regions and the trench. In addition, the dominantcrystallographic planes along the bottom 17 and sidewalls 16 of thetrench isolation regions 15 have a higher silicon density than theadjacent silicon substrate and, therefore, create a high density of trapsites along the trench bottom 17 and sidewalls 16. These trap sites arenormally uncharged but become charged when electrons and holes becometrapped in the trap sites. As a result of these trap sites formed alongthe bottom 17 and sidewalls 16 of the trench isolation regions 15,current generation near and along the trench bottom 17 and sidewalls 16can be very high and can reduce the photogenerated charge otherwiseavailable from light captured by the photodevice. Current generated fromtrap sites inside or near the photodiode depletion region also causesundesired dark current.

Minimizing dark current in the photodiode is important in CMOS imagesensor fabrication. Dark current is generally attributed to leakage inthe charge collection region 21 of the pinned photodiode 11, which isstrongly dependent on the doping implantation conditions of the CMOSimage sensor. In addition and as explained above, defects and trap sitesinside or near the photodiode depletion region strongly influence themagnitude of dark current generated. In sum, dark current is a result ofcurrent generated from trap sites inside or near the photodiodedepletion region, surface leakage at silicon/surface interface;band-to-band tunneling induced carrier generation as a result of highfields in the depletion region; junction leakage coming from the lateralsidewall of the photodiode; and leakage from isolation corners, forexample, stress induced and trap assisted tunneling.

CMOS imagers also typically suffer from poor signal to noise ratios andpoor dynamic range as a result of the inability to fully collect andstore the electric charge collected in the region 26. Since the size ofthe pixel electrical signal is very small due to the collection ofphotons in the photo array, the signal to noise ratio and dynamic rangeof the pixel should be as high as possible.

There is needed, therefore, an improved CMOS imager that exhibitsreduced pixel spacing between adjacent pixel sensor cells, reducedcross-talk and blooming, as well as reduced dark current and increasedphotodiode capacitance. There is also needed an isolation region for aCMOS imager and that (i) has minimum width to increase the pixel fillfactor (pixel density) while providing electrical and physicalseparation between photosensitive elements of adjacent pixels of theCMOS imager; (ii) prevents current generation or current leakage; and(iii) acts as a reflective barrier to electrons generated by lightabsorption in a photodiode back to the charge collection region of thephotodiode of a pixel sensor cell.

A method of fabricating active pixel photosensors exhibiting theseimprovements is also needed, as well as an isolation technique thateliminates dark current and reduces cross-talk between adjacent pixelsensor cells of a CMOS imager.

BRIEF SUMMARY OF THE INVENTION

In one aspect, the invention provides a barrier implanted region of afirst conductivity type formed in lieu of an isolation region of a pixelsensor cell that provides physical and electrical isolation ofphotosensors of adjacent pixel sensor cells of a CMOS imager. Thebarrier implanted region comprises a first region having a first widthand a second region located below the first region and having a secondwidth greater than the first width. The first region is laterally spacedfrom doped regions of a second conductivity type of adjacent photodiodesof pixel sensor cells of a CMOS imager. The first region has a width ofless than about 0.4 microns, preferably of less than about 0.2 microns,which provides minimum spacing between elements of adjacent pixel cells,such as between photosensors of adjacent pixel cells, and improves thepixel density of the CMOS imager.

The second region of the barrier implanted region is located below andin contact with the first region and has a width greater than the firstwidth, of about 0.6 to about 1.2 microns, more preferably of about 0.8microns. The first and second regions of the barrier implanted regionare formed by conducting a plurality of implants of the firstconductivity type at different energies and doping levels below thesubstrate surface.

In another aspect, the invention provides a method of forming a barrierimplanted region below a substrate surface of a CMOS imager and adjacentphotosensors of pixel sensor cells. The barrier implanted region isformed by (i) conducting a first implant to form a first implantedregion having a first width of less than about 0.4 microns, preferablyof less than about 0.2 microns, below the substrate surface; and (ii)conducting a second implant to form a second implanted region below thefirst implanted region and having a second width of about 0.6 to about1.2 microns, more preferably of about 0.8 microns.

These and other features and advantages of the invention will be moreapparent from the following detailed description that is provided inconnection with the accompanying drawings and illustrated exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of an exemplary conventional CMOS image sensorpixel.

FIG. 2 is a schematic cross-sectional view of the CMOS image sensor ofFIG. 1 taken along line 2-2′.

FIG. 3 is a schematic cross-sectional view of a CMOS image sensor pixelillustrating the fabrication of a barrier implanted region in accordancewith the present invention and at an initial stage of processing.

FIG. 4 is a schematic cross-sectional view of the CMOS image sensorfragment of FIG. 3 at a stage of processing subsequent to that shown inFIG. 3 and in accordance with an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of the CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 4.

FIG. 6 is a schematic cross-sectional view of the CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 5.

FIG. 7 is a schematic cross-sectional view of the CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 6.

FIG. 8 is a schematic cross-sectional view of the CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 7.

FIG. 9 is a schematic cross-sectional view of the CMOS image sensorpixel of FIG. 3 at a stage of processing subsequent to that shown inFIG. 8.

FIG. 10 illustrates a schematic diagram of a computer processor systemincorporating a CMOS image sensor fabricated according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as asemiconductor-based material including silicon, silicon-on-insulator(SOI) or silicon-on-sapphire (SOS) technology, doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a “wafer” or “substrate” in thefollowing description, previous process steps may have been utilized toform regions or junctions in or over the base semiconductor structure orfoundation. In addition, the semiconductor need not be silicon-based,but could be based on silicon-germanium, silicon-on-insulator,silicon-on-sapphire, germanium, or gallium arsenide, or othersemiconductor materials.

The term “pixel” refers to a picture element unit cell containing aphotosensor and transistors for converting electromagnetic radiation toan electrical signal. For purposes of illustration, portions ofrepresentative pixels are illustrated in the figures and descriptionherein and, typically, fabrication of all imager pixels in an imagerwill proceed simultaneously in a similar fashion.

The term “minimally spaced” refers to the minimal distance between atleast two adjacent pixels spaced from one another in accordance with theembodiments of the present invention. For purposes of the presentinvention, the term “minimally spaced” refers to a distance of less thanabout 0.4 microns, preferably of less than about 0.2 microns.

Referring now to the drawings, where like elements are designated bylike reference numerals, FIGS. 3-9 illustrate exemplary embodiments ofmethods of forming barrier implanted region 200 located below thesurface of substrate 110 and adjacent charge collection regions 126, 126a of photosensors formed as photodiodes 188, 188 a, of adjacentfour-transistor (4T) pixel sensor cells 100, 100 a (FIG. 9). Asexplained in detail below, the barrier implanted region 200 is formed byimplanting dopants of a first conductivity type at different energiesand/or dosages below the surface of p-type epitaxial (epi) layer 110 ato form a first implanted region 199 having a first width, and a secondimplanted region 299 having a second width greater than the first width.The second implanted region 299 is located below the first implantedregion and connects the first implanted region to the upper surface ofP+ substrate 110 b, providing therefore reduced cross-talk betweenadjacent pixels and reduced blooming.

It should be noted that, although the invention will be described belowin connection with use in a four-transistor (4T) pixel cell, theinvention also has applicability to any CMOS imager including, forexample, a three-transistor (3T) cell which differs from the 4T cell inthe omission of a charge transfer transistor, and to pixel cells havingmore than four transistors.

FIGS. 3-9 illustrate a substrate 110 along a cross-sectional view whichis the same view as in FIG. 2. For exemplary purposes, FIGS. 3-9illustrate the substrate 110 as comprising an epitaxial layer supportedby a base semiconductor. If a p+ epitaxial substrate layer is desired, ap-type epitaxial (epi) layer 110 a (FIG. 3) is formed over a highlydoped P+ substrate 110 b, as illustrated in FIG. 3. The p-type epitaxiallayer 110 a may be formed to a thickness of about 2 microns to about 12microns, more preferably of about 2 microns to about 7 microns, and mayhave a dopant concentration in the range of about 1×10¹⁴ to about 5×10¹⁶atoms per cm³, more preferably of about 5×10¹⁴ to about 5×10¹⁵ atoms percm³. The P+ substrate 110 b is a highly doped substrate with anelectrical resistivity of about 0.001 Ω-cm to about 1 Ω-cm, morepreferably of about 0.01 Ω-cm to about 0.1 Ω-cm.

FIG. 3 also illustrates multi-layered transfer gate stacks 130, 130 aformed over the p-type epitaxial layer 110 a, each corresponding tofirst and second adjacent pixel regions A and B, respectively. Theelements of the transfer gate stack 130 are similar to those of thetransfer gate stack 130 a and thus, for simplicity, a description ofonly the elements of the gate stack 130 is provided below.

The transfer gate stack 130 comprises a first gate oxide layer 131 ofgrown or deposited silicon oxide on the p-type epitaxial layer 110 a, aconductive layer 132 of doped polysilicon or other suitable conductormaterial, and a second insulating layer 133, which may be formed of, forexample, silicon oxide (silicon dioxide), nitride (silicon nitride),oxynitride (silicon oxynitride), ON (oxide-nitride), NO (nitride-oxide),or ONO (oxide-nitride-oxide). The first and second insulating layers131, 133 and the conductive layer 132 may be formed by conventionaldeposition and etching methods, for example, blanket chemical vapordeposition (CVD) or plasma enhanced chemical vapor deposition (PECVD),followed by a patterned etch, among many others.

If desired, a silicide layer (not shown) may be also formed in themulti-layered gate stack 130, between the conductive layer 132 and thesecond insulating layer 133. Advantageously, the gate structures of allother transistors in the imager circuit design may have thisadditionally formed silicide layer. This silicide layer may be titaniumsilicide, tungsten silicide, cobalt silicide, molybdenum silicide, ortantalum silicide. The silicide layer could also be a barrierlayer/refractory metal such as TiN/W or WN_(X)/W or it could be entirelyformed of WN_(X).

Reference is now made to FIG. 4. Subsequent to the formation of the gatestacks 130, 130 a, a first photoresist layer 167 is formed over thestructure of FIG. 3 to a thickness of about 1,000 Angstroms to about50,000 Angstroms. The first photoresist layer 167 is patterned to obtaina first opening 168 over an area 101 (FIG. 4) of the p-type epitaxiallayer 110 a between the adjacent pixels where a first implanted regionwill be formed in accordance with an embodiment of the presentinvention. As illustrated in FIG. 4, the first photoresist layer 167 ispatterned so that, on one side of the first opening 168, the photoresistlayer 167 extends by a distance “W₁/2” within each of the first andsecond pixel regions A and B. Preferably, the distance W₁ is of lessthan about 0.4 microns, more preferably less than about 0.2 microns,which represents the width W₁ of the first implanted region 199 (FIG.6).

Next, the structure of FIG. 4 is subjected to a first dopantimplantation 169 (FIG. 5) with a dopant of the first conductivity type,which for exemplary purposes is p-type. This way, p-type ions areimplanted through opening 168 and into area 101 of the p-type epitaxiallayer 110 a to form a first p-type well region 199 (or a first implantedregion 199), as illustrated in FIG. 6. The first p-type well region 199extends below surface 11 a of the p-type epitaxial layer 110 a, and islocated adjacent active areas A and B of the substrate 110 where twoadjacent photodiodes are to be formed, as will be described below. Thedepth into the substrate 110, shown as thickness T₁ (FIG. 6), of thefirst p-type well region 199 is of about 0.5 to about 2 microns, morepreferably of about 1 micron.

The dopant implantation 169 is conducted to implant p-type ions, such asboron or indium, into area 101 of the p-type epitaxial layer 110 a toform the first p-type well region 199 (FIG. 6). The ion implantation 169may be conducted at an energy of 50 keV to about 1 MeV, more preferablyof about 100 keV to about 500 keV. The implant dose in the first p-typewell region 199 is within the range of about 5×10¹¹ to about 5×10¹³atoms per cm², and is preferably within the range of about 1×10¹² toabout 5×10¹² atoms per cm². If desired, multiple implants may be used totailor the profile of the first p-type well region 199. In addition, theimplant or the multiple implants forming the first p-type well region199 may be angled or used in connection with at least one angledimplant.

Subsequent to the formation of the first p-type well region 199 shown inFIG. 6, the first patterned photoresist 167 is removed by conventionaltechniques, such as oxygen plasma for example. The structure at thispoint is depicted in FIG. 6.

A second masked dopant implantation is conducted with a dopant of thefirst conductivity type, which for exemplary purposes is p-type, toimplant ions in the area of the substrate directly beneath, and incontact with, the first p-type well region 199 and to form a secondp-type well region 299, as illustrated in FIG. 8. For this, a secondphotoresist layer 267 (FIG. 7) having a thickness of about 13,000Angstroms to about 100,000 Angstroms is formed over the structure ofFIG. 6 and patterned to obtain a second opening 268, as shown in FIG. 7.As illustrated in FIG. 7, the second photoresist layer 267 is patternedso that, on one side of the second opening 268, the photoresist layer267 extends by a distance “W₂/2” within each of the first and secondpixel regions A and B. Preferably, the distance W₂ is of about 0.6 toabout 1.2 microns, more preferably of about 0.8 microns, and representsthe upper width W₂ of the second implanted region 299 (FIG. 8). Asshown, the width W₂ of the opening 268 is wider than the width W₁ of theopening 168.

The second dopant implantation 269 is conducted to implant p-type ions,such as boron or indium, into area 102 of the p-type epitaxial layer 110a to form the second p-type well region 299 (FIG. 8). The second dopantimplantation 269 may be conducted by placing the substrate 110 in an ionimplanter and implanting appropriate p-type dopant ions through theopening 268. The ion implantation 269 may be conducted at an energy of50 keV to about 3 MeV, more preferably of about 200 keV to about 1.5MeV. The implant dose in the second p-type well region 299 may be thesame as or different from the implant dose in the first p-type wellregion 199. For exemplary purposes only, the implant dose in the secondp-type well region 299 is within the range of about 5×10¹¹ to about5×10¹³ atoms per cm², and is preferably within the range of about 1×10¹²to about 5×10¹² atoms per cm². If desired, multiple implants may be usedto tailor the profile of the second p-type well region 299. In addition,the implant or the multiple implants forming the second p-type wellregion 299 may be angled or used in connection with at least one angledimplant.

As illustrated in FIG. 8 and according to an exemplary embodiment, thesecond p-type well region 299 has a trapezoidal cross-section with upperwidth W₂ of about 0.6 to about 1.2 microns, more preferably of about 0.8microns, and lower width W₃ of about 0.8 to about 1.4 microns, morepreferably of about 1.0 micron. However, the invention also contemplatesthe second p-type well region 299 having other various cross-sectionalshapes, for example a rectangular shape, among others. The depth intosubstrate 110 of the second p-type well region 299, indicated bythickness T₂ (FIG. 8), is of about 1.5 to about 12 microns, morepreferably of about 5 microns.

Subsequent to the second dopant implantation 269 (FIG. 7), the secondphotoresist layer 267 is removed by conventional techniques, such asoxygen plasma for example. The structure at this point is depicted inFIG. 8.

Referring now to FIG. 9, elements of photodiodes 188, 188 a offour-transistor (4T) pixel sensor cells 100, 100 a are next formedadjacent the first and second p-type implant regions 199, 299 of thebarrier implanted isolation region 200 of the present invention.Although the invention will be described below with reference to aphotodiode as a photosensitive element, the invention is not limited tothis exemplary embodiment and contemplates the formation of theimplanted region 200 adjacent various photosensitive elements such asphotoconductor and photogates, among others.

According to an exemplary embodiment of the invention, each of thephotodiodes 188, 188 a is a p-n-p photodiode formed by regions 124, 124a, p-type epitaxial layer 110 a, and regions 126, 126 a, respectively.The n-type region 126, 126 a (FIG. 9) is formed by implanting dopants ofa second conductivity type, which for exemplary purposes is n-type, inthe area of the substrate directly beneath the active areas A and B ofthe adjacent pixel cells, and adjacent the barrier implanted region 200.As shown in FIG. 9, the n-type region 126, 126 a is spaced from thefirst p-type well region 199 by a distance “d₂” of about 10 to about 20nm in the horizontal direction. Although FIG. 9 illustrates the n-typeregion 126, 126 a slightly spaced from the first p-type well region 199,the invention is not limited to this embodiment and also contemplatesthe formation of n-type region 126, 126 a adjacent and touching thefirst p-type well region 199 in at least one side.

Further, although FIG. 9 illustrates the n-type region 126, 126 aslightly spaced from the second p-type well region 299 by a distance“d₁” of about 100 to about 500 nm, more preferably of about 300 nm, inthe vertical direction, the invention also contemplates the embodimentaccording to which the second p-type well region 299 contacts the n-typeregion 126, 126 a in at least one direction (for example, in thevertical direction) or in both vertical and horizontal directions.

The implanted n-doped region 126, 126 a forms a photosensitive chargestorage region for collecting photogenerated electrons. Ion implantationmay be conducted by placing the substrate 110 in an ion implanter, andimplanting appropriate n-type dopant ions into the substrate 110 at anenergy of 20 keV to 500 keV to form n-doped region 126, 126 a. N-typedopants such as arsenic, antimony, or phosphorous may be employed. Thedopant concentration in the n-doped region 126, 126 a (FIG. 9) is withinthe range of about 1×10¹⁵ to about 1×10¹⁸ atoms per cm³, and ispreferably within the range of about 5×10¹⁶ to about 5×10¹⁷ atoms percm³. If desired, multiple implants may be used to tailor the profile ofthe n-doped region 126, 126 a. The implants forming region 126, 126 amay also be angled implants, formed by angling the direction of implantstoward the gate stack 130, 130 a.

Another dopant implantation with a dopant of the first conductivitytype, which for exemplary purposes is p-type, is conducted so thatp-type ions are implanted into the area of the substrate over theimplanted n-type region 126, 126 a and between the transfer gate 130,130 a and the barrier implanted region 200, to form a p-type pinnedsurface layer 124, 124 a of the now completed photodiode 188, 188 a(FIG. 9).

The p-type pinned surface layer 124, 124 a is also formed by conductinga dopant implantation with a dopant of the first conductivity type,which for exemplary purposes is p-type, so that p-type ions areimplanted into the area of the substrate over the implanted n-typeregion 126, 126 a and between the transfer gate 130, 130 a and thebarrier implanted region 200.

FIG. 9 also illustrates n-type floating diffusion region 129, 129 alocated adjacent the multi-layered gate stack 130, 130 a and oppositethe n-type doped region 126, 126 a of the p-n-p photodiode 188, 188 a.This way, the multi-layered transfer gate stack 130, 130 a transferscharge accumulated in the charge collection region 126, 126 a of thephotodiode 188, 188 a to the floating diffusion region 129, 129.

The barrier implanted isolation region 200 of FIG. 9 adjacent the n-typeregion 126, 126 a acts as a reflective barrier to electrons generated bylight in the n-doped regions 126, 126 a of the p-n-p photodiodes 188,188 a. When light radiation in the form of photons strikes the photositeregions 126, 126 a, photo-energy is converted to electrons which arestored in the n-doped region 126, 126 a. The absorption of light createselectron-hole pairs. For the case of an n-doped photosite in a p-well ora p-type epitaxial layer, it is the electrons that are stored. For thecase of a p-doped photosite in an n-well, it is the holes that arestored. Thus, in the exemplary embodiment described above havingn-channel devices formed in the p-type epitaxial layer 110 a, thecarriers stored in the n-doped photosite region 126, 126 a areelectrons. The barrier implanted isolation region 200 acts to reducecarrier loss to the substrate 110 by forming a concentration gradientthat modifies the band diagram and serves to reflect electrons backtowards the n-doped photosite region 126, 126 a, thereby reducingcross-talk between adjacent pixel sensor cells.

In addition to providing a reflective barrier to electrons generated bylight in the charge collection region, the barrier implanted isolationregion 200 provides photosensor-to-photosensor isolation, for example,isolation of the p-n-p photodiode 188 from an adjacent photodiode (suchas adjacent p-n-p photodiode 188 a) located on the other side of thebarrier implanted region 200.

In addition to providing a barrier region and photosensor-to-photosensorisolation, the barrier implanted isolation region 200 also eliminatesthe formation of shallow trench isolation regions and, therefore, theformation of trap sites along the bottom of such shallow trenchisolation regions. As a result of eliminating the formation of thesetrap sites along the bottom of the trench isolation regions, darkcurrent generation and leakage is decreased. The barrier implantedregion 200 also “hooks-up” the p-type epitaxial layer 110 a to the P+substrate 110 b to minimize cross-talk, and allows for improved pixelscaling.

The remaining devices of the pixel sensor cell 100, 100 a, including thereset transistor, the source follower transistor and row selecttransistor shown in FIG. 1 as associated with respective gates 40, 50and 60 and source/drain regions on either sides of the gates, are alsoformed by well-known methods. Conventional processing steps may be alsoemployed to form contacts and wiring to connect gate lines and otherconnections in the pixel cell 100, 100 a. For example, the entiresurface may be covered with a passivation layer of, e.g., silicondioxide, BSG, PSG, or BPSG, which is CMP planarized and etched toprovide contact holes, which are then metallized to provide contacts tothe reset gate, transfer gate and other pixel gate structures, asneeded. Conventional multiple layers of conductors and insulators toother circuit structures may also be used to interconnect the structuresof the pixel sensor cell.

A typical processor based system 600, which has a connected CMOS imager642 having pixels constructed according to the invention is illustratedin FIG. 10. A processor based system is exemplary of a system havingdigital circuits which could include CMOS image sensors. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system and data compression system forhigh-definition television, all of which can utilize the presentinvention.

A processor based system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 644, for example, amicroprocessor, that communicates with an input/output (I/O) device 646over a bus 652. The CMOS image sensor 642 also communicates with thesystem over bus 652. The computer system 600 also includes random accessmemory (RAM) 648, and, in the case of a computer system may includeperipheral devices such as a floppy disk drive 654, and a compact disk(CD) ROM drive 656 or a flash memory card 657 which also communicatewith CPU 644 over the bus 652. It may also be desirable to integrate theprocessor 654, CMOS image sensor 642 and memory 648 on a single IC chip.

Although the above embodiments have been described with reference to theformation of photosensors as p-n-p photodiodes of adjacent pixel cells,such as the p-n-p photodiode 188, 188 a (FIG. 9) having n-type chargecollection regions 126, 126 a formed adjacent p-type barrier implantedregion 200, it must be understood that the invention is not limited tothis embodiment. Accordingly, the invention has equal applicability toother photosensors including n-p-n photodiodes comprising p-type chargecollection regions formed adjacent an n-type barrier implanted region,photogates and other types of photosensors. Of course, the dopant andconductivity type of all structures will change accordingly, with thetransfer gate corresponding to a PMOS transistor. Further, although theembodiments of the present invention have been described above withreference to a p-n-p photodiode, the invention also has applicability ton-p or p-n photodiodes.

In addition and as noted above, although the invention has beendescribed with reference to the formation of only one barrier implantedisolation region 200 isolating charge collection regions ofphotosensitive elements of adjacent pixel sensor cells, the inventionalso contemplates the formation of a multitude of such barrier implantedregions located at various locations on the substrate to isolate pixels.Further, although the invention has been described above with referenceto a transfer gate of a transfer transistor connection for use in afour-transistor (4T) pixel cell, the invention also has applicability toa five-transistor (5T) pixel cell, a six-transistor (6T) pixel cell, ora three-transistor (3T) cell, among others.

The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

1. A pixel structure comprising: a substrate; an isolation region of afirst conductivity type located below a surface of said substrate, saidimplanted region comprising at least two implanted isolation regionshaving different widths; and at least one photosensor having a chargecollection region of a second conductivity type formed adjacent saidimplanted isolation region.
 2. The pixel structure of claim 1, whereinsaid photosensor is a photodiode.
 3. The pixel structure of claim 1,wherein said photosensor is a photoconductor.
 4. The pixel structure ofclaim 1, wherein said photosensor is a photogate.
 5. The pixel structureof claim 1, wherein said pixel comprises two photosensors, each disposedon opposite sides of said implanted region and adjacent said implantedregion.
 6. The pixel structure of claim 1, wherein said substratefurther comprises a doped epitaxial layer over a substrate layer, andwherein said implanted region is provided within said doped epitaxiallayer.
 7. The pixel structure of claim 6, wherein said implanted regioncomprises a first implanted isolation region located below an uppersurface of said doped epitaxial layer, said first implanted isolationregion having a first width, and a second implanted isolation regionlocated below and in contact with said first implanted isolation region,said second implanted isolation region having a second width greaterthan the first width.
 8. The pixel structure of claim 7, wherein saidfirst width is less than about 0.4 microns.
 9. The pixel structure ofclaim 8, wherein said first width is less than about 0.2 microns. 10.The pixel structure of claim 7, wherein said second width is about 0.6to about 1.2 microns.
 11. The pixel structure of claim 10, wherein saidsecond width is about 0.8 microns.
 12. The pixel structure of claim 7,wherein said first implanted isolation region has a thickness of about0.5 to about 2.0 microns.
 13. The pixel structure of claim 12, whereinsaid first implanted isolation region has a thickness of about 1 micron.14. The pixel structure of claim 7, wherein said second implantedisolation region has a thickness of about 1.5 to about 12.0 microns. 15.The pixel structure of claim 14, wherein said second implanted isolationregion has a thickness of about 5 microns.
 16. The pixel structure ofclaim 7, wherein said second implanted isolation region has atrapezoidal cross-section.
 17. The pixel structure of claim 7, whereinsaid first implanted isolation region is doped with a p-type dopant at adopant concentration of from about 5×10¹¹ to about 5×10¹³ atoms per cm².18. The pixel structure of claim 17, wherein said first implantedisolation region is doped with a p-type dopant at a dopant concentrationof about 1×10¹² to about 5×10¹² atoms per cm².
 19. The pixel structureof claim 7, wherein said second implanted isolation region is doped witha p-type dopant at a dopant concentration of from about 5×10¹¹ to about5×10¹³ atoms per cm².
 20. The pixel structure of claim 19, wherein saidsecond implanted isolation region is doped with a p-type dopant at adopant concentration of about 1×10¹² to about 5×10¹² atoms per cm². 21.The pixel structure of claim 1, wherein said implanted isolation regionis located within a p-type epitaxial layer formed over a P+ substrate.22. The pixel structure of claim 21, wherein said p-type epitaxial layeris formed to a thickness of about 2 to about 12 microns.
 23. The pixelstructure of claim 22, wherein said p-type epitaxial layer is formed toa thickness of about 2 to about 7 microns.
 24. The pixel structure ofclaim 1, wherein said first conductivity type is p-type and said secondconductivity type is n-type.
 25. The pixel structure of claim 1, whereinsaid first conductivity type is n-type and said second conductivity typeis p-type.
 26. The pixel structure of claim 1, wherein said photosensoris a p-n-p photodiode.
 27. A pixel structure comprising: a substrate; animplanted region of a first conductivity type located below a surface ofsaid substrate; and a first and second photosensors formed adjacent saidimplanted region and on opposite sides of said implanted region, saidfirst photosensor being spaced from said second photosensor by less thanabout 0.4 microns.
 28. The pixel structure of claim 27, wherein saidfirst photosensor is spaced from said second photosensor by less thanabout 0.2 microns.
 29. The pixel structure of claim 27, wherein saidimplanted region comprises at least two implanted isolation regionshaving different widths, said at least two implanted isolation regionsbeing located one below the other and in contact with each other. 30.(canceled)
 31. (canceled)
 32. An isolation structure formed in asubstrate for isolating a first pixel sensor cell from an adjacentsecond pixel sensor cell, said isolation structure comprising: a firstimplanted region of a first conductivity type extending below an uppersurface of a substrate, said first conductivity type being complementaryto a second conductivity type first and second charge collection regionscorresponding to said first and second pixel sensor cells, respectively,said first implanted region having a first width; and a second implantedregion located below and in contact with said first implanted region,said second implanted region having a second width greater than thefirst width.
 33. (canceled)
 34. (canceled)
 35. The isolation structureof claim 32, wherein said first width is less than about 0.4 microns.36. (canceled)
 37. The isolation structure of claim 32, wherein saidsecond width is about 0.6 to 1.2 microns.
 38. (canceled)
 39. Theisolation structure of claim 32, wherein said first implanted region hasa thickness of about 0.5 to about 2.0 microns.
 40. The isolationstructure of claim 32, wherein said second implanted region has athickness of about 1.5 to about 12.0 microns.
 41. (canceled)
 42. Theisolation structure of claim 41, wherein said doped epitaxial layer isformed to a thickness of about 2 to about 12 microns.
 43. The isolationstructure of claim 42, wherein said doped epitaxial layer is formed to athickness of about 2 to about 7 microns.
 44. (canceled)
 45. (canceled)46. (canceled)
 47. An imaging device, comprising: a first photosensor ofa first pixel cell, said first photosensor comprising a first dopedlayer of a first conductivity type formed in a substrate, and a firstcharge collection region formed below said first doped layer foraccumulating photo-generated charge, said charge collection region beingof a second conductivity type; a second photosensor of a second pixelcell, said second photosensor comprising a second doped layer of saidfirst conductivity type formed in said substrate, and a second chargecollection region formed below said second doped layer for accumulatingphoto-generated charge, said charge collection region being of saidsecond conductivity type; and a barrier implanted region of said firstconductivity type located adjacent both said first and secondphotosensors for providing isolation of said first photosensor from saidsecond photosensor, said barrier implanted region comprising at leasttwo different isolation regions having different widths.
 48. The imagingdevice of claim 47, wherein said barrier implanted isolation regioncomprises a first isolation region having a first width of less thanabout 0.2 microns, and a second isolation region located below and incontact with said first isolation region and having a second width ofabout 0.8 microns.
 49. (canceled)
 50. The imaging device of claim 48,wherein each of said first and second isolation regions is doped with ap-type dopant at a dopant concentration of from about 5×10¹¹ to about5×10¹³ atoms per cm².
 51. The imaging device of claim 50, wherein eachof said first and second isolation regions is doped with a p-type dopantat a dopant concentration of from about 1×10¹² to about 5×10¹² atoms percm².
 52. (canceled)
 53. (canceled)
 54. The imaging device of claim 48,wherein each of said first and second charge collection regions isadjacent a respective gate of a transfer transistor formed over saidsubstrate, said transfer gate transferring charge accumulated inrespective first and second charge collection regions to a respectivefirst and second doped region of said second conductivity type. 55.(canceled)
 56. A CMOS image sensor comprising: a p-type epitaxial layerprovided over a P+ substrate; a p-type barrier implanted isolationregion formed within said p-type epitaxial layer; and a first pixeladjacent said p-type barrier implanted region and comprising a firstphotosensor, and a second pixel adjacent said p-type barrier implantedregion and comprising a second photosensor, wherein said firstphotosensor is spaced from said second photosensor by less than about0.2 microns.
 57. The CMOS image sensor of claim 56, wherein said p-typebarrier implanted region comprises a first p-type well region having afirst width and a second p-type well region located below and in contactwith said first p-type well region, said second p-type well regionhaving a second width which is greater than the first width.
 58. TheCMOS image sensor of claim 57, wherein said first p-type well region isin contact with an upper surface of said p-type epitaxial layer, andsaid second p-type well region is in contact with an upper surface ofsaid P+ substrate.
 59. The CMOS image sensor of claim 57, wherein saidfirst p-type well region has a thickness of about 0.5 to about 2.0microns.
 60. (canceled)
 61. The CMOS image sensor of claim 57, whereinsaid second p-type well region has a thickness of about 1.5 to about12.0 microns.
 62. (canceled)
 63. (canceled)
 64. (canceled) 65.(canceled)
 66. (canceled)
 67. A CMOS imager system comprising: (i) aprocessor; and (ii) a CMOS imaging device coupled to said processor,said CMOS imaging device comprising: an implanted region of a firstconductivity type formed in a substrate, said implanted regioncomprising at least two implanted isolation regions having differentwidths; and at least two pixels adjacent said implanted region, each ofsaid pixels comprising a photodiode adjacent a gate of a transfertransistor, each of said photodiodes further comprising a pinned layerof said first conductivity type, and a doped region of a secondconductivity type located below said pinned layer, said doped regionbeing adjacent said implanted region.
 68. The system of claim 67,wherein each of said photodiodes is a p-n-p photodiode.
 69. The systemof claim 67, wherein said at least two implanted isolation regionscomprise a first implanted isolation region having a width less thanabout 0.2 microns and a second implanted isolation located below and incontact with said first implanted region.
 70. The system of claim 67,wherein said at least two pixels are spaced from one another by lessthan about 0.2 microns.
 71. A method of forming pixel sensor cells, saidmethod comprising: providing a first doped layer of a first conductivitytype in a substrate; forming at least one barrier implanted isolationregion in said doped layer to isolate said pixel sensor cells, saidbarrier implanted isolation region comprising a first well region of afirst width and a second well region of a second width greater than thefirst width, the second well region being located below and in contactwith the first well region; forming at least two charge collectionregions of a second conductivity type in said first doped layer, saidcharge collection regions being adjacent said barrier implantedisolation region; and forming at least two second doped layers of saidfirst conductivity type in said substrate above each of said chargecollection regions.
 72. The method of claim 71, wherein said first dopedlayer is a p-type epitaxial layer.
 73. The method of claim 71, whereinsaid first well region is formed to a width of less than about 0.4microns.
 74. The method of claim 73, wherein said first well region isformed to a width of less than about 0.2 microns.
 75. The method ofclaim 71, wherein said second well region is formed to a width of about0.6 to about 1.2 microns.
 76. The method of claim 75, wherein saidsecond well region is formed to a width of about 0.8 microns.
 77. Themethod of claim 71, wherein said first well region is formed to athickness of about 0.5 to about 2 microns.
 78. The method of claim 77,wherein said first well region is formed to a thickness of about 1micron.
 79. The method of claim 71, wherein said second well region isformed to a thickness of about 1.5 to about 12.0 microns.
 80. The methodof claim 79, wherein said second well region is formed to a thickness ofabout 5 microns.
 81. The method of claim 71, wherein said first wellregion is doped with a p-type dopant at a dopant concentration of fromabout 5×10¹¹ to about 5×10¹³ atoms per cm².
 82. The method of claim 81,wherein said first well region is doped with a p-type dopant at a dopantconcentration of about 1×10¹² to about 5×10¹² atoms per cm².
 83. Themethod of claim 71, wherein said second well region is doped with ap-type dopant at a dopant concentration of from about 5×10¹¹ to about5×10¹³ atoms per cm².
 84. The method of claim 83, wherein said secondwell region is doped with a dopant at a dopant concentration of about1×10¹² to about 5×10¹² atoms per cm².
 85. The method of claim 71,wherein pixel sensor cells are spaced from each other by less than 0.4microns.
 86. The method of claim 85, wherein pixel sensor cells arespaced from each other by less than 0.2 microns.
 87. A method of formingminimally spaced pixel cells of an imaging device, said methodcomprising: forming an implanted region below a surface of a p-typeepitaxial layer by implanting p-type ions within said p-type epitaxiallayer, said implanting region being formed of a first p-type well regionhaving a first width and a second p-type well region having a secondwidth greater than the first width; and providing at least two n-typedoped regions of photosensitive elements of at least two pixel cellsbelow said surface of said p-type epitaxial layer and adjacent saidimplanted region.
 88. The method of claim 87, wherein said p-typeepitaxial layer is formed over a P+ substrate layer.
 89. The method ofclaim 88, wherein said first p-type well region is formed below saidsurface of said p-type epitaxial layer, and wherein said second p-typewell region is formed below and in contact with said first p-type wellregion and in contact with an upper surface of said P+ substrate layer.90. The method of claim 87, wherein said first p-type well region isformed to a width of less than about 0.4 microns.
 91. (canceled)
 92. Themethod of claim 87, wherein said second p-type well region is formed toa width of about 0.6 to about 1.2 microns.
 93. (canceled)
 94. The methodof claim 87, wherein said first p-type well region is formed to athickness of about 0.5 to about 2 microns.
 95. The method of claim 87,wherein said second p-type well region is formed to a thickness of about1.5 to about 12.0 microns.
 96. (canceled)
 97. (canceled)
 98. A method offorming an isolation structure for isolating pixel sensor cells, saidmethod comprising: providing an epitaxial layer over a doped substrate,said epitaxial layer being doped with dopants of a first conductivitytype; conducting a plurality of implants with dopants of said firstconductivity type in said epitaxial layer to form an implanted isolationregion having a at least a first doped isolation region and a seconddoped isolation region located below and in contact with said firstdoped isolation region, said second doped isolation region having asecond width greater than a first width of said first doped isolationregion; and forming doped regions of photosensors of a secondconductivity type in said epitaxial layer, said photosensors beingadjacent said implanted region.
 99. The method of claim 98, wherein alower portion of said second doped isolation region contacts an uppersurface of said doped substrate.
 100. The method of claim 98, whereinsaid first doped isolation region is formed to a width of less thanabout 0.4 microns.
 101. The method of claim 98, wherein said first dopedisolation region is formed to a width of less than about 0.2 microns.102. (canceled)
 103. (canceled)
 104. (canceled)